The knowledge to catch design failures before they reach the test chamber
Most hardware failures that reach the test chamber were visible earlier - in the schematic, or in the layout. The knowledge to catch them exists: in standards, application notes, test reports from the last project, and in the judgment of senior engineers. What's missing is a systematic way to apply that knowledge before the board goes to fab.
Schematic checks can flag a missing decoupling cap or an absent TVS diode. What they can't do is reason about whether those components are correct for the circuit they're protecting. They don't know whether the TVS clamping voltage is right for the connected IC's absolute maximum, whether the decoupling is sized for that power domain's transient behaviour, or whether the filter topology matches what the interface actually requires. That level of review requires understanding what each part of the circuit is doing, not just that a component is present.
Engentica applies EMC, signal integrity, and power integrity rules to schematics and PCB layouts. Findings are explained, not just flagged - so engineers can investigate and resolve issues without waiting for a senior review or a test report.
Founded by Andy Eadie, an EMC and hardware engineer.
Andy has trained EMC and hardware engineers at organisations including ABB, Philips, SGS, Tata Consultancy, and others through EMC FastPass.
What we believe
Most EMC failures are preventable at design time
The evidence is nearly always in the schematic or layout before the board is built. The problem is finding it systematically rather than by experience.
PCB-level EMC compliance is a solved problem
The knowledge exists - in application notes, textbooks, and training courses. What has always been missing is having that knowledge present at the point of design, in the full context of the circuit being reviewed. That is what Engentica provides.
Understanding what a circuit does matters more than knowing how it's connected
Standard DRC operates on connectivity. Good EMC review requires knowing the topology, the interface type, the power domain behaviour - what the circuit is actually doing.
Expert knowledge should reach every engineer, not just those with access to an expert
EMC expertise is scarce and unevenly distributed. The goal is to make it available at the moment it's relevant, in every design, regardless of who's reviewing it.
Team knowledge shouldn't leave when engineers do
EMC expertise earned through failures, re-spins, and hard-won experience belongs in the review process - not in one person's head. Expertise packs let teams encode that knowledge so it surfaces automatically on every design, for every engineer.
Good tooling augments judgment, it doesn't replace it
The right role for a tool is decision support - surfacing the right context so engineers can make better calls faster, not making the calls for them.
We're working with a small number of hardware teams through our Design Partner Program - co-developing the platform with teams who are dealing with the same problems. If that's you, we'd like to talk.